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TSMC introduces new 5nm manufacturing process to increase wafer production

TSMC introduces new 5nm manufacturing process to increase wafer production
27 Oct, 2021

The world’s largest semiconductor manufacturer Taiwan Semiconductor Manufacturing Company (TSMC) has introduced a new manufacturing process called N4P that, the company claims, will bring enhancements in performance, power efficiency and process complexity in manufacturing of 5nanometer (nm) chips. 

The addition of a new node/process will allow TSMC to offer more manufacturing options to its customers and OEM partners. 

The company claims that the N4P process will result in an 11% performance boost over N5 process and a 6% boost over N4. N4P will also improve power efficiency by 22% and transistor density by 6% in comparison to N5. Further, TSMC said, N4P will reduce process complexity and improve wafer cycle time by reducing the number of masks. 

According to TSMC, N4P process was designed to enable easy migration of 5nm platform-based products, so it can enable their customers to deliver faster and more power efficient refreshes. The new process apparently improves wafer production time, which could be very good news for the company and its customers, which includes the who's who of electronics companies.

TSMC controls over 50% of the global pure wafer foundry market as of Q2 2021 and generated US $13.30 billion in sales during the quarter, according to Taipei-based market information firm TrendForce Corp, reported Focus Taiwan. Global semiconductor shortage that has impacted supply of electronics and automobiles is expected to continue until 2022. 

The company is also working on maximizing design compatibility between N4 and N5, to cut costs of completely porting designs to new nodes.

The first batch of products based on N4P technology are expected to tape out by the second half of 2022. Tape out is the final version of the design process for integrated circuits before they are sent for manufacturing. 

“With N4P, TSMC strengthens our portfolio of advanced logic semiconductor technologies, each with its unique blend of performance, power efficiency and cost. N4P was optimized to provide a further enhanced advanced technology platform for both HPC and mobile applications,”  Kevin Zhang, Senior Vice President of Business Development at TSMC said in a statement. 

“Between all the variants of N5, N4 and N3 technologies, our customers will have the ultimate flexibility and unmatched choice of the best mix of attributes for their products,” Zhang added.